(1) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing such a semiconductor device, and more particularly to a semiconductor device having a transistor structure capable of moving electrons or holes as a carrier at a high speed, and a method of manufacturing such a semiconductor device.
(2) Description of the Related Art
In recent years, the society is rapidly growing more and more information-intensive, and efforts are being made to make many information-processing electronic devices such as large-size computers, personal computers (PCs), personal digital assistants (PDAs), cell phones, etc. higher in operational speed and functionality and lower in power consumption. For further advancing those information-processing electronic devices, it is essential to make semiconductor devices which support the advancement as internal components also higher in operational speed and functionality and lower in power consumption.
FIG. 64 of the accompanying drawings is a schematic cross-sectional view of a basic structure of a conventional semiconductor device.
A semiconductor device 100 shown in FIG. 64 has a device-separating region 102 formed in a silicon (Si) substrate 101 and surrounding a region serving as a transistor forming region. A gate insulating film 103 and a gate electrode 104 are formed in the transistor forming region, and a low-concentration LDD (Lightly Doped Drain) region 105 and a source/drain 106 are formed in the Si substrate 101. Plugs 107 are connected to the source/drain 106 and also to interconnection layers 108, thus providing the semiconductor device 100. If necessary, a well region is formed in the Si substrate 101.
Heretofore, it has been customary to improve the performance of transistors by reducing the size of gate electrodes. However, since enormous facility investments are required to reduce the size of gate electrodes and limitations will sometimes be posed on attempts to reduce the size of gate electrodes, there have been efforts to improve the performance of transistors without reducing the size of gate electrodes. Conventional semiconductor devices according to first through third examples for the purpose of improving the performance of transistors are shown in FIGS. 65 through 67 of the accompanying drawings.
FIG. 65 is a schematic cross-sectional view of a semiconductor device according to a first conventional example. In FIG. 65, those elements which are identical to those shown in FIG. 64 are denoted by identical reference numerals.
A semiconductor device 200 shown in FIG. 65 is different from the semiconductor device 100 shown in FIG. 64 in that a silicone germanium (SiGe) layer 201 is formed by epitaxial growth on the surface region of the Si substrate 101 where a channel is formed. Other structural details of the semiconductor device 200 are identical to those of semiconductor device 100. Si and SiGe have different lattice constants, the lattice constant of SiGe being greater than the lattice constant of Si. However, because SiGe is formed as a thin layer on Si, SiGe is formed with the same lattice constant as Si. Such a structure is called “strained SiGe structure”, and has a hole mobility about twice greater than if only the Si substrate 101 were used.
FIG. 66 is a schematic cross-sectional view of a semiconductor device according to a second conventional example. In FIG. 66, those elements which are identical to those shown in FIGS. 64 and 65 are denoted by identical reference numerals.
A semiconductor device 300 shown in FIG. 66 is different from the semiconductor device 200 shown in FIG. 65 in that a SiGe layer 201 and an Si layer 301 are successively formed by epitaxial growth on the Si substrate 101 and the uppermost Si layer 301 is used as a transistor channel. Other structural details of the semiconductor device 300 are identical to those of semiconductor device 200 according to the first example. With the semiconductor device 300 according to the second example, SiGe is deposited by way of epitaxial growth on the Si substrate 101, forming the SiGe layer 201. Though SiGe has the same lattice constant as Si insofar as the film thickness of SiGe is small in an initial growth state, SiGe comes to have its inherent lattice constant as its thickness increases (relaxed SiGe layer). When a thin layer of Si is formed by epitaxial growth on the relaxed SiGe layer, Si is formed with the same lattice constant as SiGe contrary to the strained SiGe structure. Such a structure is called “strained Si structure”, and has an electron mobility about twice greater than if only the Si substrate 101 were used and a hole mobility about several tens % greater than if only the Si substrate 101 were used.
FIG. 67 is a schematic cross-sectional view of a semiconductor device according to a third conventional example. In FIG. 67, those elements which are identical to those shown in FIG. 64 are denoted by identical reference numerals.
A semiconductor device 400 shown in FIG. 67 is different from the semiconductor devices 200, 300 according to the first and second examples which utilize a strain developed due to different lattice constants. In the semiconductor device 400, an insulating film 401 is formed in the Si substrate 101 near the gate electrode 104. Forces tending to spread the Si substrate 101 are produced by stresses that are generated when the insulating film 401 is expanded or contracted in a heat treatment process. In this manner, the channel region of the transistor is strained to increase the carrier mobility. It has been said that the electron mobility is increased several tens % by straining the channel region of the transistor with the above structure.
Heretofore, the above transistor structures based on strains have been adopted to increase the electron or hole mobility without reducing the size of the gate electrodes. However, with conventional general transistor structures, a parasitic capacitance due to a pn junction exists between the source/drain and the substrate and between the channel and the substrate, and the operation of the transistor is delayed by such a parasitic capacitance. It has strongly been desired to solve such a problem and produce high-speed, low-power-consumption transistors.
To solve the problem of the parasitic capacitance due to the pn junction, there has been proposed a semiconductor device having a cavity defined below a semiconductor layer where a source/drain and a channel are formed (for example, see Japanese Unexamined Patent Publication No. 2000-22158 (paragraph Nos. [0019] through [0025], [0035] through [0039], FIGS. 1, 3, and 4). According to this proposal, the semiconductor layer is formed above the cavity which serves as an insulating layer, providing an SOI (Silicon On Insulator) structure. By providing the cavity whose dielectric constant is lower than that of an insulating layer such as a silicon oxide (SiO2) layer formed beneath a semiconductor layer in a usual SOI structure, the capacitance between the source/drain and the substrate and the capacitance between the channel and the substrate are reduced, preventing the transistor operation from being delayed. The semiconductor device can be produced by forming a sacrificial oxide film and a semiconductor layer on a semiconductor substrate, pattering the sacrificial oxide film and the semiconductor layer to the size of the gate of a transistor to be formed, and covering the exposed portion with a protective oxide film. After forming an opening with the protective oxide film left as a side wall, an etching liquid is introduced through the opening to selectively remove the sacrificial oxide film. Thereafter, the opening is closed by an insulating film deposited according to CVD (Chemical Vapor Deposition) or sputtering. A gate electrode and a source/drain are formed on the semiconductor layer above the cavity which has been formed by removal of the sacrificial oxide film.